Course Description

This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.

This course explores Incisive? comprehensive coverage features, with which you can measure how thoroughly your testbench exercises your design. The course addresses coverage of SystemC, VHDL, Verilog?, and mixed-language designs. Not all coverage features are available with all languages.

The course discusses the collection and analysis of the following types of coverage:

• Code (block, expression, toggle, state, and arc) coverage
• Data-oriented functional coverage using SystemVerilog covergroups
• Control-oriented functional coverage using PSL and SystemVerilog assertions

Learning Objectives

After completing this course you will be able to:

• Effectively use the Incisive comprehensive coverage with your SystemC, VHDL, Verilog, and mixed-language designs

Course Description

This course addresses Incisive? mixed-language (SystemC?, VHDL, and Verilog?) event-driven digital simulation. The course takes you through the compilation, elaboration, simulation, and interactive debug process, at each step explaining the most commonly used options. This course treats the SystemC, VHDL, and Verilog languages equivalently. You can do the labs in your choice of language.

Learning Objectives

After completing this course you will be able to:

• Compile, elaborate, link, and simulate a design: Understand how to specify the inputs and outputs at each phase, configure the design, and control each process for effectiveness and optimal performance.
• Debug a design with the textual interactive simulation interface: Briefly examine most of the interactive commands for the purpose of understanding what capabilities are available and how you can use them in a script to drive batched regression tests; practice these capabilities in the context of a scripted debug scenario.
• Debug a design with the graphical interactive simulation interface: Examine many of the capabilities of the feature-rich SimVision graphical simulation analysis environment; practice these capabilities in the context of a scripted debug scenario.
• Utilize some of the other tools available to assist your simulation-related efforts to: Verify your platform's patch level, protect your intellectual property, “l(fā)int” your design and filter and sort the analysis report, manage your library of compiled design objects, compare simulation traces, package your design for transmittal, and much more.
• Optionally: Understand the issues involved with mixed-language instantiation, simulation, and debugging; examine the mechanics of interconnecting components of multiple languages; choose and simulate a mixed-language design configuration containing at least one HDL component and at least one SystemC component.